1. Technical Field
The invention relates to a voltage generating circuit of a semiconductor memory apparatus such as a NAND type flash memory, etc. Particularly, the invention relates to a voltage generating circuit for generating voltages, which are used for such as a bit line clamp voltage, etc.
2. Related Art
In a read operation of a flash memory, after a bit line is pre-charged, the bit line is separated from a sense amplifier to produce a potential corresponding to a data state of a memory cell on the bit line, and the sense amplifier is used to detect the potential of the bit line. A charge transfer transistor is connected between the bit line and the sense amplifier for controlling pre-charge of the bit line and charge transfer of the bit line. The operation of the charge transfer transistor is controlled by a clamp voltage generated by a clamp voltage generating circuit.
Generally, in order to determine data as “0” or “1”, the clamp voltage generating circuit has to generate a clamp voltage with a low level. Therefore, a conventional clamp voltage generating circuit is composed of intrinsic transistors with a low threshold value, though such type of transistors has a shortage of uneven threshold values. In order to avoid such problem, a patent document 1 discloses a clamp voltage generating circuit, in which a resistor voltage divider circuit is disposed between an input section of a current mirror circuit and a ground potential, and a potential setting circuit is disposed between an output of the resistor voltage divider circuit and an output section of the current mirror circuit, so that the clamp voltage is generated at the output section of the current mirror circuit.
Moreover, in order to prevent wrong sensing of data stored in the memory unit, a patent document 2 discloses a clamp voltage generating circuit shown in FIG. 1. As shown in FIG. 1, one end of a charge transfer transistor 30 is connected to a bit line BL, and another end thereof is connected to a sense amplifier 20. A gate of the charge transfer transistor 30 is connected to the clamp voltage generating circuit 10. The clamp voltage generating circuit 10 includes a constant current source 14, N-channel metal oxide semiconductor (NMOS) transistors 12 and 13 serving as switch devices, an NMOS transistor 15 having a same threshold voltage with that of the charge transfer transistor 30, and a variable resistor 16.
The sense amplifier 20 includes an NMOS transistor 21, a capacitor 22 and a latch circuit 23. A drain of the NMOS transistor 21 is coupled to a power node VDD/VSS, a source thereof is connected to a sensing node TDC, and the NMOS transistor 21 sets the sensing node TDC to one of a power voltage VDD and a ground voltage VSS.
In the read operation, the bit line BL is charged to a precharge voltage VPRE by the clamp voltage generating circuit 10. To be specific, the transistor 12 is turned on, and the transistor 13 is turned off A resistance value of the variable resistor 16 is set according to a manner that a voltage drop of the variable resistor 16 reaches the precharge voltage VPRE. In this way, a voltage of “VPRE+Vth” is applied to the gate of the charge transfer transistor 30 to serve as a bit line clamp voltage BLCLAMP. Now, the sensing node TDC is charged to the power voltage VDD. The charge transfer transistor 30 is turned off at a time point when the bit line BL reaches the precharge voltage VPRE.
Then, the transistor 12 is turned off, and the transistor 13 is turned on, and 0V is applied to the gate of the charge transfer transistor 30 to serve as the clamp voltage BLCLAMP, and the charge transfer transistor 30 is turned off, and the bit line BL is in a floating state. Then, a read voltage is applied to a selected word line, and a read pass voltage is applied to the non-selected word lines, and a selection transistor ST1 and a selection transistor ST2 are turned on, and a source line CELSRC, for example, has a level of 0V.
Then, the clamp voltage generating circuit 10 generates a voltage “Vsen+Vth” to serve as the clamp voltage BLCLAMP, which is implemented by setting the voltage drop of the variable resistor 16 to the sensing voltage Vsen. When the selected memory unit is turned on, the bit line BL is discharged, and the voltage of the bit line BL is below the sensing voltage Vsen, and the charge transfer transistor 30 is turned on. When the charge transfer transistor 30 is turned on, the sensing node TDC charged to the power voltage VDD discharges. The sense amplifier 20 determines the stored data of the selected memory unit to be “1”, and maintains the determination result in the latch circuit 23.